;----------------------------------------------------------------------------------------;
; Lab07
; Robert Cardona CSULB CECS 347
; Spring 2012
; Lab07.s
;
; ARM Assembly Language / Fundamentals and Techniques
; William Hohl, 1st Edition
;----------------------------------------------------------------------------------------;
; RVMDK requires a reset handler - normally found in startup.s code
; name should be "Reset_Handler" (not case sensitive)
GDR RN r4
Level RN r5
ADCR EQU 0xE0034000
ADGDR EQU 0xE0034004
ADCR_Val EQU 0x00210E08
DACREG EQU 0xE006C000
SRAM_BASE EQU 0x40000000
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000400
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; VPBDIV definitions
VPBDIV EQU 0xE01FC100 ; VPBDIV Address
VPBDIV_SETUP EQU 1
VPBDIV_Val EQU 0x01
VPBDIV_Val_0 EQU 0x00 ; One-fourth of processor clock
VPBDIV_Val_1 EQU 0x01 ; Same as processor clock
VPBDIV_Val_2 EQU 0x02 ; One-half of processor clock
; Phase Locked Loop (PLL) definitions
PLL_BASE EQU 0xE01FC080 ; PLL Base Address
PLLCON_OFS EQU 0x00 ; PLL Control Offset
PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
PLLCON_PLLE EQU (1<<0) ; PLL Enable
PLLCON_PLLC EQU (1<<1) ; PLL Connect
PLLCFG_MSEL EQU (0x04<<0) ; PLL Multiplier (M=5)
PLLCFG_PSEL EQU (0x02<<5) ; PLL Divider (P=2)
PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
PLL_SETUP EQU 1
PLLCFG_Val EQU PLLCFG_MSEL:OR:PLLCFG_PSEL ; 60Mhz
; Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 ; MAM Base Address
MAMCR_OFS EQU 0x00 ; MAM Control Offset
MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000004
; External Memory Controller (EMC) definitions
EMC_BASE EQU 0xFFE00000 ; EMC Base Address
BCFG0_OFS EQU 0x00 ; BCFG0 Offset
BCFG1_OFS EQU 0x04 ; BCFG1 Offset
BCFG2_OFS EQU 0x08 ; BCFG2 Offset
BCFG3_OFS EQU 0x0C ; BCFG3 Offset
;// <e> External Memory Controller (EMC)
EMC_SETUP EQU 0
BCFG0_SETUP EQU 0
BCFG0_Val EQU 0x0000FBEF
BCFG1_SETUP EQU 0
BCFG1_Val EQU 0x0000FBEF
BCFG2_SETUP EQU 0
BCFG2_Val EQU 0x0000FBEF
BCFG3_SETUP EQU 0
BCFG3_Val EQU 0x0000FBEF
;// </e> End of EMC
; External Memory Pins Definitions
PINSEL0 EQU 0xE002C000
PINSEL1 EQU 0xE002C004
PINSEL2 EQU 0xE002C014
PINSEL0_Val EQU 0x00000000
PINSEL1_Val EQU 0x10080000 ; PINSEL2 Address
PINSEL2_Val EQU 0x00000000 ; CS0..3, OE, WE, BLS0..3,
; D0..31, A2..23, JTAG Pins
; UART 0 Registers and Settings
UART0_BASE EQU 0xE000C000 ; UART0 Base Address
U0RBR_0FS EQU 0x00 ; Recieve Buffer Register
U0THR_0FS EQU 0x00 ; Transmit Holding Register
U0DLL_0FS EQU 0x00 ; Divisor Latch LSB (DLA=1)
U0DLM_0FS EQU 0x04 ; Divisor Latch MSB (DLA=1)
U0IER_0FS EQU 0x04 ; Interrupt Enable Register
U0IID_0FS EQU 0x08 ; Interrupt ID Register
U0FCR_0FS EQU 0x08 ; FIFO Control Register
U0LCR_0FS EQU 0x0C ; Line Control Register
U0LSR_0FS EQU 0x14 ; Line Status Register
U0SCR_0FS EQU 0x1C ; Scratch Pad Register (8-bits)
U0ACR_0FS EQU 0x20 ; Auto-Baud Control Register
U0FDR_0FS EQU 0x28 ; Fractional Divider Register
U0TER_0FS EQU 0x30 ; Tx Enable
; UART 1 Registers and Settings
UART1_BASE EQU 0xE0010000 ; UART0 Base Address
U1RBR_0FS EQU 0x00 ; Recieve Buffer Register
U1THR_0FS EQU 0x00 ; Transmit Holding Register
U1DLL_0FS EQU 0x00 ; Divisor Latch LSB (DLA=1)
U1DLM_0FS EQU 0x04 ; Divisor Latch MSB (DLA=1)
U1IER_0FS EQU 0x04 ; Interrupt Enable Register
U1IID_0FS EQU 0x08 ; Interrupt ID Register
U1FCR_0FS EQU 0x08 ; FIFO Control Register
U1LCR_0FS EQU 0x0C ; Line Control Register
U1LSR_0FS EQU 0x14 ; Line Status Register
U1SCR_0FS EQU 0x1C ; Scratch Pad Register (8-bits)
U1ACR_0FS EQU 0x20 ; Auto-Baud Control Register
U1FDR_0FS EQU 0x28 ; Fractional Divider Register
U1TER_0FS EQU 0x30 ; Tx Enable
PRESERVE8
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
; LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
; Setup External Memory Pins
IF
EF:EXTERNAL_MODE
LDR R0, =PINSEL2
LDR R1, =PINSEL2_Val
STR R1, [R0]
ENDIF
; Setup External Memory Pins
IF
EF:EXTERNAL_MODE
LDR R0, =PINSEL0
LDR R1, =PINSEL0_Val
STR R1, [R0]
ENDIF
; Setup External Memory Controller
IF EMC_SETUP <> 0
LDR R0, =EMC_BASE
IF BCFG0_SETUP <> 0
LDR R1, =BCFG0_Val
STR R1, [R0, #BCFG0_OFS]
ENDIF
IF BCFG1_SETUP <> 0
LDR R1, =BCFG1_Val
STR R1, [R0, #BCFG1_OFS]
ENDIF
IF BCFG2_SETUP <> 0
LDR R1, =BCFG2_Val
STR R1, [R0, #BCFG2_OFS]
ENDIF
IF BCFG3_SETUP <> 0
LDR R1, =BCFG3_Val
STR R1, [R0, #BCFG3_OFS]
ENDIF
ENDIF ; EMC_SETUP
; Setup VPBDIV
IF VPBDIV_SETUP <> 0
LDR R0, =VPBDIV
LDR R1, =VPBDIV_Val
STR R1, [R0]
ENDIF
; Setup PLL
IF PLL_SETUP <> 0
LDR R0, =PLL_BASE
MOV R1, #0xAA
MOV R2, #0x55
; Configure and Enable PLL
MOV R3, #PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
; Wait until PLL Locked
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
ENDIF ; PLL_SETUP
; Setup MAM
IF MAM_SETUP <> 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP
; Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IF
EF:REMAP
LDR R0, =MEMMAP
IF
EF:EXTMEM_MODE
MOV R1, #3
ELIF
EF:RAM_MODE
MOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF
EF:__MICROLIB
EXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
ENDIF
;Start of Deleted Area
;----------------------------------------------------------------------------------------;
AREA Lab02, CODE, READONLY
ENTRY
; Start Book Code
;----------------------------------------------------------------------------------------;
MAIN LDR sp, =SRAM_BASE
BL Initialize ; Initialize UART0
OLOOP MOV R6, #360
LDR r2, =ADGDR
LDR GDR, [r2]
MOV r3, #0x80000000
AND r1, r3, GDR
CMP r1, r3
BNE OLOOP
LSR GDR, GDR, #6
LDR r3, =0x3FF
MOV Level, #0x1F
AND GDR, r3, GDR
;CASES
CMP GDR, Level
LDRLS r2, =34
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =33
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =32
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =31
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =30
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =29
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =28
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =27
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =26
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =25
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =24
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =23
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =22
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =21
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =20
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =19
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =18
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =17
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =16
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =15
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =14
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =13
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =12
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =11
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =10
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =9
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =8
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =7
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =6
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =5
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =4
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =3
BLS ILOOP
ADD Level, Level, #0x1F
CMP GDR, Level
LDRLS r2, =2
BLS ILOOP
LDR r2, =1
ILOOP RSB R1, R6, #360
BL SIN
MOV R0, R0, ASR#16
MOV R0, R0, LSL#9
MOV R0, R0, ASR#15
ADD R0, R0, #512
MOV R0, R0, LSL#6
STRH R0, [R8]
SUBS R6, R6, R2
CMP R6, #0x00
BGT ILOOP
B OLOOP
SIN STMIA sp!, {R4, R5, R7, lr}
MOV R7, R1
LDR R5, =270
ADR R4, SIN_DATA
CMP R1, #90
BLE RET_VAL
CMP R1, #180
RSBLE R1, R1, #180
BLE RET_VAL
CMP R1, R5
SUBLE R1, R1, #180
BLE RET_VAL
RSB R1, R1, #360
RET_VAL LDR R0, [R4, R1, LSL #2]
CMP R7, #180
RSBGT R0, R0,#0
LDMDB sp!, {R4, R5, R7, pc}
Initialize STMIA sp!, {r0, r1, r2, r3, r5, r6, r7, lr}
LDR R0, =PINSEL0
LDR R1, =PINSEL0_Val
STR R1, [R0]
LDR R0, =PINSEL1
LDR R1, =PINSEL1_Val
STR R1, [R0]
LDR r8, =DACREG
LDR R0, =ADCR
LDR R1, =ADCR_Val
STR R1, [R0]
LDMDB sp!, {r0, r1, r2, r3,r5, r6, r7, pc}
ALIGN
SIN_DATA
DCD 0x00000000, 0x023be164, 0x04779630, 0x06b2f1d8
DCD 0x08edc7b0, 0x0b27eb50, 0x0d613050, 0x0f996a30
DCD 0x11d06ca0, 0x14060b80, 0x163a1a80, 0x186c6de0
DCD 0x1a9cd9c0, 0x1ccb3220, 0x1ef74c00, 0x2120fb80
DCD 0x234815c0, 0x256c6f80, 0x278dde80, 0x29ac3780
DCD 0x2bc750c0, 0x2ddf0040, 0x2ff31bc0, 0x32037a40
DCD 0x340ff240, 0x36185b00, 0x381c8bc0, 0x3a1c5c80
DCD 0x3c17a500, 0x3e0e3dc0, 0x40000000, 0x41ecc480
DCD 0x43d46500, 0x45b6bb80, 0x4793a200, 0x496af400
DCD 0x4b3c8c00, 0x4d084600, 0x4ecdff00, 0x508d9200
DCD 0x5246dd00, 0x53f9be00, 0x55a61280, 0x574bb900
DCD 0x58ea9100, 0x5a827980, 0x5c135380, 0x5d9cff80
DCD 0x5f1f5f00, 0x609a5280, 0x620dbe80, 0x63798500
DCD 0x64dd8900, 0x6639b080, 0x678dde80, 0x68d9f980
DCD 0x6a1de700, 0x6b598f00, 0x6c8cd700, 0x6db7a880
DCD 0x6ed9ec00, 0x6ff38a00, 0x71046d00, 0x720c8080
DCD 0x730baf00, 0x7401e500, 0x74ef0f00, 0x75d31a80
DCD 0x76adf600, 0x777f9000, 0x7847d900, 0x7906c080
DCD 0x79bc3880, 0x7a683200, 0x7b0a9f80, 0x7ba37500
DCD 0x7c32a680, 0x7cb82880, 0x7d33f100, 0x7da5f580
DCD 0x7e0e2e00, 0x7e6c9280, 0x7ec11a80, 0x7f0bc080
DCD 0x7f4c7e80, 0x7f834f00, 0x7fb02e00, 0x7fd31780
DCD 0x7fec0a00, 0x7ffb0280, 0x7fffffff
;----------------------------------------------------------------------------------------;
; End Book Code
END ;End of Deleted Area